Programmable interconnections
Hardware implementation
Hardware is implemented as a regular template of spiking neurons. This template is in the same spirit as FPGAs, except that analog neurons replace logic gates. Interconnections between neurons can be implemented either with direct physical connections (power efficient), or with virtual connections using the Adress-Event Representation (AER) scheme (high degree of flexibility), or a combination of both.
Physical (left) or virtual (right) implementations of neural interconnections.
CAD tools for architecture exploration
In order to evaluate the performance of interconnections architectures, we develop Computer-Aided Design (CAD) tools that automatically place and route the neural applications onto the architecture under investigation. Automated architecture exploration routines can then be used to identify the best options.
